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TU Darmstadt is one of Germany's leading technical institutions, where the Electrical Engineering department is ranked 4th nationwide in employer reputation according to the WirtschaftsWoche 2023 University Ranking. Combining high academic rigor with cutting-edge technical output, the program's research capacity is backed by top tier placement, including a Top 3 national ranking for Systems research output on CSRankings

Through my 10 year academic journey, I built a solid theoretical and analytical foundation, beginning with two years of intensive study in mathematics and physics that shaped my quantitative reasoning. This groundwork was then expanded through a Bachelor's degree and two Master's degrees, giving me a broad technical background across hardware and software engineering. This background can be summarized in the following three main pillars:

(Grades index: ◉ very good grade ◉ good grade)

Pillar 1: Analog HW

Analog IC design ◉: (link)
- MOS Resistors, MOS Switch and MOS Diode
- Current Sinks and Sources
- Current Mirrors
- Current and Voltage References
- Temperature Independent (Bandgap) References
- Operational Amplifiers
  - Single stage amplifiers
  - multi stage amplifiers
  - ac-coupled multistage amplifier
    - Voltage gain, input and output resistances, current and power gain
  - dc-coupled multistage amplifier
    - DC analysis
    - AC analysis
  - Darlington circuit
  - MOS Differential amplifiers
  - MOS Output Stage Amplifiers
  - Amplifier Frequency Response
  - Direct Determination of the Low-Frequency Poles and Zeros
  - Estimation of ωL Using the Short-Circuit Time-Constant Method
  - Transistor Models at High Frequencies
  - High Frequency Limitations of Single-Stage Amplifiers

Miller Multiplication

Estimation of ωH Using the Open-Circuit Time-Constant Method
Single-Pole Operational-Amplifier Compensation
Slew Rate of an Operational Amplifier
The two stage Opamp
Two stage Miller Opamp
Design procedure of the two stage Miller Opamp
Cascode Opamps
Comparator
Two stage Comparator
Other comparator architectures

Pillar 2: Digital HW

SoC:
- SoC infrastructure & topologies
- peripheries (IOs, Timer, PWM, UART, I2C, SPI, CAN, LIN, USB, Ethernet...)
- Memory types and their internal circuits
FPGA ◉ (link)
- FPGA internal items (CLB, Slice, LUT, MUX...)
- FPGA programming (Verilog/Bluespec)
- Routing elements&Architectures
- Internal SRAM, RAM, clock manager...
Digital IC Design ◉ (link)
- Short Channel Effects
- CMOS Inverter
- CMOS Technologies
- Static CMOS Logic
- Passtransistor and Transmission Gate Logic
- Memory elements and dynamic logic
- Performance- Interconnect and Packaging
- Digital Subsystem Design
- DACs and ADCs
- Finite State Machines
- Gate Arrays
CAD for SoC ◉ (Link)
- SoC Xilinx
- Cadence Virtuoso
- standard Cell design
- Transistor Level simulation
- Floorplanning
- Verilog/Verilog-AMS
- Routing / Placement
GCRA (Coarse Gain Reconfigurable Architecture) ◉ (link)
- PE Structure (ALU, MUX, Registers..)
- CGRA Structure (PE Array, Context Unit, Memory, conditions box)
- Binding and Allocations
- Scheduling (dynamic & static):
  - ASAP- ALAP- List- ILP- BULB-, Simulated Annealing- Forced directed- Rotation based- interactive ILP- Scheduling
- Data/Control Flow graph
- Control memory data flow graph

Pillar 3: Software

SW Languages:
- Java, Python, C++, C, Verilog, Angular, Bluespec, Assembly

Software engineering ◉ (link1, link2)
- Petri Network
- Data flow Analysis
- Control flow Analysis
- Waterfall model & V model
- SQL / OCL
- Unified Modeling Language (ULM)
Parallel computing ◉ (link)
- Algorithms
- Multithreading OpenMP
- GPGPU computing, CUDA
Machine learning basics ◉ (link)
Software defined network basics ◉ (SDN)
- SDN Data/Control/application Plane
- Virtualization and Slicing
Communication protocols (link1 ,link2):